The present invention generally relates to telecommunication systems and more particularly to frame alignment or frame synchronization of a digital link.
A digital link is generally considered as an interface between entities of a telecommunication network. In particular, a digital link could be an interface between a switch core and units such as multiplexors, and exchange terminals. Data are transmitted on the digital link in time slots that are arranged into frames. When several data channels are multiplexed onto a single transmission facility one of the challenges is to determine the boundary of the frames within the overall combined stream of transmitted data. For the receiving equipment to interpret the data properly, the receiving hardware needs a way of distinguishing the beginning and end of each frame. This is called frame-level synchronization or frame alignment.
A known and common synchronization approach is to have a unique sequence of bits, called frame alignment word (FAW), located at the beginning of each frame. With this basic and simple technique a single starting flag, i.e. the FAW, will allow synchronization.
However, it is desirable to minimize the buffering of information and therefore the frame alignment word (possibly with additional overhead) is interleaved, usually bit by bit, at equidistant intervals together with the payload in the frame. This technique is particularly useful when dealing with large frames.
In general, frames of interleaved payload and overhead are continuously transmitted between entities that are in communication with each other. At lost frame alignment in one of the interconnected entities, that entity starts searching for the interleaved FAW in the frame being received from the other entity, and gains frame alignment upon detection of the FAW.
In this context, a fast frame alignment technique consists in storing a relatively long sequence of payload and interleaved overhead data in a large serial register. In principle, the length of this sequence has to be such that the sequence is capable of containing the complete frame alignment word in its interleaved form. Assume, by way of example, that the overhead is interleaved with payload in such a way that 1 bit of overhead is followed by 11 bits of payload and so on. According to this example, the register must be capable of storing data of at least 12 times the length of the FAW. The stored data bits are evaluated in order to find the frame alignment word. If the FAW is not found in the stored sequence, a next sequence is read and evaluated and so on until the FAW is found. At most, this procedure will require a whole frame before frame alignment is accomplished. The main disadvantage with this prior art technique is that a hardware realization requires a considerable amount of logic circuitry.
Another commonly used technique is to utilize a register of the same length as the frame alignment word itself, in which every n:th bit of the interleaved bit flow is stored, starting at bit x. Here, n represents the interleaving distance. If the FAW is not found in a complete frame, the wrong bits have been considered, and the process is repeated starting at x+1. If the FAW is recovered, then the frame boundary is found; otherwise the process starts over again at x+2 et cetera. In the worst case scenario, this approach will require n complete frames to find the frame alignment word.
U.S. Pat. No. 5,420,865 issued to Swanbery discloses a method and system for aligning non-interleaved frames in start-stop communication between two devices. An all 1's pattern is employed to cause a device that is misaligned to inform the other device of this condition in such a way that the other device is caused to transition into the misaligned state. In addition, all 1's patterns are also used to cause a device in the misaligned state to transition into a realignment state. When in the realignment state the device transmits an end of alignment sequence, which acts as frame alignment word, to cause the other device to transition into an aligned state.